1. Field of the Invention:
The present application relates generally to semiconductor circuit structures and methods, and more specifically to a method for fabricating a DRAM cell capacitor and the structure formed thereby.
2. Description of the Prior Art:
Dynamic random access memories (DRAMs) are formed using cells having a single transistor and one capacitor. To enhance device performance, the capacitance of the capacitor should be made as large as possible. This can be accomplished by increasing the plate area of the capacitor, decreasing the plate spacing, or increasing the dielectric constant of the dielectric between plates.
Given a best available dielectric constant for the dielectric and minimum plate spacing, increased capacitance is achieved by increasing the plate area of the capacitor. Thus, the capacitor should occupy a space which is as large as possible on the surface of the DRAM. However, in order to achieve high density for the device, it is necessary to shrink the individual cell size as much as possible. This tends to decrease the capacitor plate area, thereby decreasing capacitance.
Several different approaches have been taken to increase the available capacitor plate area within the constraints of a minimal cell size. One approach is to form capacitor plates along vertical sidewalls, such as along the sidewalls of a trench cut into a substrate. A second approach is to form the capacitor above certain device features such as bit lines and transfer gates. This approach allows capacitors to cover a larger percentage of the surface area of each DRAM cell. Examples of the second approach can be found in the following papers: A NEW STACKED CAPACITOR DRAM CELL CHARACTERIZED BY A STORAGE CAPACITOR ON A BITLINE STRUCTURE, 1988 IEDM Proceedings, pages 596-599; and STACKED CAPACITOR CELLS FOR HIGH-DENSITY DYNAMIC RAMS, 1988 IEDM Proceedings, pages 600-603.
A third approach, which can be combined with the second approach just described, is to form a multiple plate capacitor. This provides more plate area, and hence capacitance, for a given cell layout area. An example of such approach is described in 3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS, 1988 IEDM Proceedings, pages 592-595. The device structure described in this paper forms layers of storage node capacitor fins interdigitated with ground plate fins.
The method for forming a multiple plate capacitor in the paper cited above is cumbersome, and it is difficult to verify the quality of the capacitor formed using that technique. As shown in FIG. 1 of the cited paper, it is necessary to etch away intermediate layers from between the storage node capacitor plates, form a dielectric, and then form the capacitor ground plates between the different storage node plates. It is difficult to ensure the quality of the dielectric and ground node plates in the small spaces between the storage node plates.
It would be desirable to provide a method for providing a high capacitance capacitor consistent with current process technologies. It would further be desirable for such a capacitor to be reliable.